Maximization of storage capacity and minimization of power usage and access time are goals in the design of integrated circuits (ICs, "chips"), especially as to ICs containing memory and logic arrays for use in data processing systems.
I. Row Decoder Design
To increase the storage capacity of a random access memory (RAM), it is important to find ways to reduce the amount of area occupied by circuitry other than the storage cell arrays of the RAM. One way in which this can be accomplished is by utilizing a shared row decoder design which permits wordlines in both left and right units of a bank division of the RAM to be accessed through the same set of row decoders, thus decreasing by half the number of row decoders required to perform that function. However, this goal is not well served if the reduction in decoder circuitry is made at the expense of increased access time or higher power consumption for the RAM, especially in cases where the design for a RAM chip requires a plurality of banks.
FIG. 1 shows an example of a 32 Mb double unit 10 which includes left and right units 12, 20, left and right wordline (WL) driver units 14, 18, and a shared row decoder unit 16 which receives inputs including row predecoded addresses XP1 . . . XPn, and block select inputs BLKSELs. This 32 Mb double unit organization has been incorporated into an existing design for a 256 Mb DRAM, the details of which are described in the Article by Y. Watanabe et al. entitled "A 286 mm2 256 Mb DRAM with .times.32 Both-Ends DQ," IEEE Journal of Solid-State Circuits, Vol. 31, No. 4, April, 1996 ("the Watanabe Article"). Within the shared row decoder unit 16 there are provided a plurality of row decoders 30, the structure of which is shown in FIG. 2.
As shown in FIG. 2, each row decoder 30 of shared row decoder unit 16 (FIG. 1) receives as inputs a plurality of row predecoded addresses, for example three predecoded addresses (XP1, XP2, XP3), and a block select signal BLKSEL. Upon receiving the correct combination of row predecoded addresses XPs to enable the row decoder 30 at a time when the BLKSEL signal is active, the row decoder 30 activates a row decoder output signal RDOUT which is provided to both a left WL driver 14 and a right WL driver 18 of the double unit 10. In this way, only one row decoder 30 is needed to enable the selection of blocks from both left and right units, 12, 20.
In operation, the BLKSEL signal is held active during a time in which both units 12, 20 are in an active state. During a reset phase, when the BLKSEL signal enters an inactive state again, RDOUT signals of row decoders 30 are precharged to HIGH, at which time units 12, 20 are simultaneously deactivated.
It will be understood that the row predecoded addresses XPs must hold the information constant for the duration in which BLKSEL is active. Otherwise, RDOUT might be falsely enabled by the XPs transition between states because the XPS provide the enabling and trigger conditions for RDOUT.
Because the row decoder 30 requires the XPs to hold the information constant during BLKSEL active cycles, it is not possible to use row decoder unit 30 in a double unit 10 in which it is desired to utilize each unit 12, 20 as a separate bank under separate row addressing control. That is, row decoder 30 cannot be used in a double unit 10 which is configured to operate as two or more banks.
FIG. 3 shows a schematic for the design of another existing row decoder unit 40 which permits a pair of left and right units 12, 20 to be configured as a pair of banks, rather than just a single bank, as is the conventional configuration. Row decoder unit 40 includes sets of row decoder circuits 42 for each of the left unit 12 and the right unit 20 which are completely independent from each other, i.e. the decoder circuits 42 in each set include independent devices which receive and act upon the row predecoded addresses and block select signals to activate wordlines within the respective left and right units, 12, 20. Consequently, left and right units 12, 20 can each be independently controlled, to access storage locations at different row addresses at the same time.
However, row decoder unit 40, which duplicates the input and output circuits for all predecoded address and block select inputs, requires twice the number of row predecoded address signal lines and row decoder circuits 42 as row decoder unit 16. In consequence, the area occupied by row decoder unit 40 on an IC is substantially greater than the area occupied by row decoder unit 16. It would be advantageous to provide a row decoder unit which permits a double unit to be configured with multiple banks, without requiring row decoder circuits therein to be duplicated.
Accordingly, it is an object of the invention to provide a row decoder circuit of a row decoder unit which permits a plurality of banks to be configured within a pair of memory units, i.e. a pair of physically contiguous memory arrays served by the row decoder unit, while reducing the amount of area occupied by the row decoder unit.
It is another object of the invention to provide a row decoder unit which reduces the consumption of current while permitting a double unit to be configured as multiple banks.
II. Block Address Assignment Within Banks
In an existing RAM (as shown, for example, in FIG. 1), blocks are arranged in the same way within left and right units 12, 20, namely, numbered in sequential order from bottom to top (or from top to bottom). As such, blocks which are accessed by the same address inputs are located across from each other at the same distance away from the ends 22 of the units 12, 20. That is, block 0 in the left unit 12 is located across from block 0 in the right unit 20 and lies at the end 22 of the left unit 12, as does block 0 in the right unit 20. In the same way, block 1 in the left unit is located across from block 1 in the right unit 20 and lies one block away from the end 22 of the left unit 12, as does block 1 in the right unit 20.
However, the inventors have found that addressing blocks within the left and right units 12, 20 in such symmetrical fashion is undesirable. Within a unit 12, one or more wordlines in a block are activated at a time by signals supplied to the row decoder from one end 22 of the unit 12. As described above with reference to FIG. 3, units 12, 20 can be accessed independently in an ACTIVE mode when double unit 10 is configured as multiple banks, each bank having independent row decoder circuits 42. However, when double unit 10 is configured as a single bank, units 12, 20 are not independently controlled, such that the row decoder unit 16 accesses the same physical block numbers across both units 12, 20. Even when the double unit 10 is configured as multiple banks, when the double unit 10 is operated in known Column-Address-Strobe (CAS) Before Row-Address-Strobe (RAS) Refresh mode (CBR mode), locations will be accessed within each unit 12, 20 with signals selecting the same block numbers in both units 12, 20.
Thus, in CBR mode, whether in a single bank unit or in a double unit having a multiple bank configuration, wordlines in the same numbered blocks in both left and right units 12, 20 are alternately or simultaneously accessed, first from one unit, for example, the left unit 12, then from the other unit, i.e. the right unit 20 in this example.
When high numbered blocks are accessed, e.g block 15 in the left and right units 12, 20, the greater length of signal travel (and consequent voltage drop) from the end 22 of the units 12, 20 to such blocks requires more current to be supplied than that required to access low-numbered blocks located closer to the end 22 of the left and right units 12, 20, i.e. block 0 in each unit. Thus, in the existing arrangement of blocks, the current consumption within a double unit 10 varies with the address of the block selected for access. Likewise, the average voltage drop on row selection signal lines to both units 12, 20 (e.g. row predecoded addresses and block select signals) varies with the address of the block selected for access. In addition, heating effects due to the consumption of current vary with both time and with the location of a block within a bank.
Accordingly, an object of the invention is to provide an arrangement of blocks within a double unit which reduces or eliminates the dependence of the current consumption, heating effects and average voltage drop upon the address of the block which is accessed.
III. Column Address Increment Design
The need to increase density while decreasing the power consumption of RAMs for applications such as laptop computers imposes limitations upon the speed at which cells within a RAM can be accessed. However, these on-chip considerations must not be allowed to unduly limit the speed of off-RAM access, since otherwise, the off-RAM access speed could become a bottleneck in the performance of the computing system which utilizes the RAM.
One known way of increasing the off-RAM access speed in synchronous dynamic RAMs (DRAMs) is to perform a modified column burst mode operation in which sequentially adjacent addresses are accessed simultaneously from an "odd" column division (left unit) and an "even" column division (right unit) of a bank, rather than merely providing addresses to the left unit and to the right unit in sequence, as described above with reference to FIG. 1. To perform such operation, the lowest order bits of the column address are transferred to one of the odd/even units after being incremented by one, and transferred directly without being incremented to the other one of the odd/even units. Such operation is referred to a "column address increment". An example of a circuit design which performs such operations is described in an article by Yukinori Kodama et al. entitled "A 150 MHz 4-Bank 64 Mbit SDRAM with Address Incrementing Pipeline Scheme," 1994 Symposium on VLSI Circuits Digest of Technical Papers, pp. 81-82 ("the Kodama Article").
The Kodama Article describes a design for a DRAM which performs column address increment to transfer data to and from a storage locations within a bank at twice the access speed of the storage cells within. In that design, each bank is configured as a double memory unit (e.g. as in FIG. 1; 10) having left and right units 12, 20 separated from each other by row decoder circuitry for the bank. Left and right units 12, 20 form odd and even units of the bank which are accessed with consecutive column addresses that are provided simultaneously to both odd and even units. The row decoder circuitry between left and right units 12, 20 decodes a set of row selection signals and activates, at the same time, wordlines in both left and right units 12, 20 in accordance with to the decoding result. A similar concept is discussed in U.S. Pat. No. 5,386,385 to Stephens, Jr.
The Kodama Article, and the Stephens, Jr. Patent describe systems which implement column address increment pipelining, but only in a double unit 10 which is configured as a single bank, i.e. with a left unit 12 implementing an "odd" unit, and a right unit 20 implementing an "even" unit. The Kodama Article and the Stephens, Jr. Patent do not describe a way in which column address increment could be implemented in a double unit 10 which is configured as multiple banks. A way of providing column address increment pipelining in a double unit 10 having any number of banks therein would be desirable.
Accordingly, it is an object of the invention to provide a structure and method of providing column address increment pipelining in a double unit 10 in which more than one odd unit and one even unit are configured within the same unit (e.g. unit 12, or unit 20) and in which wordlines are supported by the same set of row decoders and wordline driver circuitry.
Another object of the invention is to provide a structure and method of providing column address increment operation simultaneously in each bank of a plurality of banks configured within a double unit 10.
IV. Read Write Drive Design
Towards the goal of increasing the speed of memory access while holding the line on or reducing the power consumption, it is important to transmit large current bearing signals within the RAM as efficiently as possible. Therefore, designs which reduce: 1) the amount of current needed to drive large current signals; 2) the number of signals being driven; or 3) the frequency at which large current signals switch between low and high levels, are desirable to reduce the power consumption while increasing the access speed of the RAM.
In an existing RAM described in the Watanabe Article referred to above, and as shown in detail in FIG. 4, data is transferred to and from a DRAM storage array 400 by a circuit arrangement and signal flow known as "master DQ" (MDQ) architecture. The detailed schematic of storage array 400 in FIG. 4 corresponds to the internal organization of unit 12 or 20 of FIG. 1. Within the storage array 400, as provided by the MDQ architecture, data is passed from bitline pairs within the storage array 400 by a hierarchical arrangement of local DQ lines (LDQs) and master DQ lines (MDQs). A data input output circuit (DIO) 490 is coupled to the storage array 400 by a second sense amplifier unit (SSA) 450. SSA 450 receives data signals on master bitline pairs (MDQs) of the storage array 400, regenerates the data and transmits it again onto bidirectional read write drive lines (RWD, RWD') 480 to the DIO 490.
When accessing the storage array 400 during column burst mode operation in which several adjacent column storage locations are accessed sequentially, the amount of current required to perform such operation is known as the column burst current. The largest single contributor to the column burst current is the current needed to drive the RWD and RWD' lines 480 in transmitting data between the second sense amplifier (SSA) 450 and the data input/output circuit (DIO) 490.
With reference to FIG. 4b, signal levels on either line RWD, or line RWD' 480 are driven, in every clock cycle of the DIO 490, between an (inactive) precharge voltage level and an (active) data level. Regardless of the data pattern, large current is required to drive the rapid swing between the precharge voltage level and the active data level in the presence of large capacitive loads 460, 461.
It would be desirable to have a circuit and method of signal transmission which reduces the amount of current needed to drive signals between the second sense amplifier 450 and the data input/output circuit 490. Reducing the number of signal lines RWD, RWD' for each data bit from two to one, and eliminating the precharge cycle on the RWD signal line would greatly reduce the amount of current required to drive a high capacitive load 460 coupled to the signal line.
Accordingly, it is an object of the invention to provide a second sense amplifier circuit and signal arrangement by which data is transmitted from a second sense amplifier to a data input/output circuit with less current than with existing second sense amplifier designs.
It is another object of the invention to provide a second sense amplifier circuit which outputs data onto a single read write drive signal, in place of two read write drive signals.
It is a further object of the invention to provide a circuit and method of signal transmission which reduces the rate at which voltage levels of the read write drive signal are switched.
Still another object of the invention is to provide a circuit and method of signal transmission by which data bits are transmitted sequentially on a read write drive signal without requiring the signal line to be precharged between each data bit.